Virtual test head for IC

ABSTRACT

In a test system for a semiconductor device, the device under test (DUT) is remotely located relative to the tester that generates the test vector signals. The tester and remotely located DUT are connected by a serial connection and each includes a serializer-deserializer for converting outgoing data to serial form and deserializing incoming data.

FIELD OF THE INVENTION

The invention relates to the testing of semiconductor devices.

BACKGROUND OF THE INVENTION

It is common in the semiconductor field to test and analyze defectivechips in order to pinpoint the cause of a problem. Various types offailure analysis (FA) tools have been developed to examine/inspect thedevice under test (DUT) and pinpoint the location or region on the DUTwhere the problem occurs from photon emission or secondary electronacquisition or physical probing, etc. For example, some FA tools knownin the art include EMMI (Emmission Microscopy), pico-probe stations, IDS(electron beam prober) and sem (electron microscope). While the DUTs arephysically being viewed by one of these tools, the FA tools requirephysical access to the DUT for purposes of viewing the die surface and,in the case of a pico-probe station, to physically probe the DUT. Thisexamination of the DUT is therefore done in a lab where the FA tools arelocated.

However, in addition to evaluating the DUT by physically inspecting theregions of the chip while signals are applied to the DUT, faults in aDUT are also pinpointed by simply applying signals to the pins orcertain test nodes on the DUT and analyzing the output signals from theoutput pins of the chip. This type of analysis is thus purely electricalin nature and involves the generation of test vector pattern data thatis fed into the chip. The test vectors are applied to the chip by atester, which is depicted in the system block diagram of FIG. 1 byreference numeral 100. Typically the program that comprises the testvector pattern is loaded from a server 102 where the program is stored,and access is commonly provided to a user (the test engineer) at aclient station 104 (typically a personal computer (PC)) The tester 100is provided with a test head, which includes a motherboard 108 with asocket 106 for supporting the DUT. The test head typically contains ahigh speed DRAM buffer for loading input data and output data. The DUT110 is shown in FIG. 1, mounted in the socket 106. In the case of apackaged device with 18 I/O or clock pins, 18 electrical connectionswill typically have to be made between the mother board 108 and thesocket 106 on which the device under test 110 (DUT) is mounted. Outputdata from the output pins of the DUT is sent to the tester 100 and canbe analyzed by the user at the client 104, which is connected to thetester 100, typically via an intranet connection.

In practice, the tester on which the DUT is mounted is commonly placedon top of the FA tool (e.g. in the case where the DUT has to be placedin a vacuum chamber of the FA tool) or in close proximity to the FA tool(e.g., in the case where the FA tool comprises a microscope for viewingthe DUT). One such FA tool/tester combination is shown in FIG. 2, whichshows a tester 200 with its motherboard, 202 and socket 204, supportinga DUT 206. Mounted over the tester 200 is an FA tool 210 in the form ofa microscope. This close proximity causes problems for the analysis doneusing the FA tool since, the tester with its many data lines and coolingequipment causes a fair amount of vibration, which interferes with theFA tool analysis. In fact, it is not uncommon for a DUT to have manymore than just 18 pins. Typical testers may have sockets with 512, 756,or 1024 I/O pins and an equivalent number of data lines between themotherboard and the socket.

The present invention seeks to address this problem.

Furthermore, even if the test engineer who ultimately performs the testis remotely located at a client station such as client 104 shown in FIG.1, the systems known in the art still require a person to be present inthe lab to place the DUT in the tester even in the absence of FA toolanalysis, if the DUT is simply being electronically tested using testvectors.

The present invention seeks to provide a more convenient solution incases where chips are tested purely electronically by means of testvector pattern data.

SUMMARY OF THE INVENTION

According to the invention, there is provided a method of testing asemiconductor device (DUT) comprising, separating the DUT from thetester and mounting the DUT remotely on a virtual tester, which may belocated in the test engineer's office. The tester, which is typicallystill located in a lab, includes a first adaptor means for communicatingwith the remote DUT via a second adaptor means. The tester may stillincludes a test head with a motherboard having a socket. However,instead of placing the DUT in the socket of the motherboard, the socketnow receives the first adaptor means. The first adaptor means mayinclude an adaptor board mountable on the socket. The adaptor boardpreferably includes a serializer-deserializer (SERDES) for seriallytransmitting test vector pattern data to the remotely located secondadaptor means and for serially receiving output data from the DUT. Theremotely located DUT is, in turn, mounted on the second adaptor means(which typically also includes a serializer-deserializer (SERDES)) forserially receiving and transmitting information with the first adaptormeans.

Accordingly the invention includes a method of testing a semiconductordevice (DUT) using a tester, comprising locating the DUT at a locationremote from the tester, and providing communication means for the testerand the DUT for transferring information between the tester and the DUT.Typically the information transferred from the tester to the DUT is testvector pattern data, and the information transferred from the DUT to thetester is output data from output pins of the DUT. The tester and DUTmay be connected by an intranet or Internet connection, and providingthe communication means typically includes providing a firstserializer-deserializer (SERDES) located at the tester and providing asecond SERDES located at the DUT. The tester may include a motherboardwith a socket, wherein the method includes mounting the first SERDES onthe socket of the motherboard. The DUT and second SERDES may, in turn,be mounted on a printed circuit board, wherein the printed circuit boardmay include a socket for mounting the second SERDES.

Further, according to the invention, there is provided a method ofreducing vibration to a DUT being evaluated by a failure analysis toolwhile signals are provided to the DUT by a tester, comprising placingthe tester sufficiently far from the failure analysis tool to eliminateor significantly reduce the vibration, and communicating seriallybetween the tester and the DUT.

Still further, according to the invention, there is provided a testerfor testing semiconductor devices, comprising a test vector generatorand a data communication means, wherein the data communication meansincludes a SERDES for converting test vector pattern data generated bythe tester to serial form for serial transmission to a remotely locatedDUT and for deserializing DUT output data received from the remote DUT.Typically the tester is connected to the DUT by a serial connection suchas an intranet or the Internet.

Still further, according to the invention, there is provided a virtualtest head, which comprising means for mounting a DUT and means fordeserializing incoming test vector pattern data and serializing outgoingdata from the output pins of the DUT. The virtual test head may alsoinclude circuitry for selectively tri-stating lines to the pins of theDUT. The virtual test head may also include circuitry for generating aclock signal and for selectively applying the clock signal to one ormore of the pins of the DUT.

For purposes of this application, output pins includes pins thataccommodate bidirectional data (bidirects). Also for purposes of thisapplication I/O pins is used to refer to all I/O pins whether they areinput, output or bidirects. The virtual test head may include a printedcircuit board (PCB) and the SERDES is preferably mounted on the PCB. Thetool may include a motherboard supporting a socket for mounting the PCB.The fault analysis tool may include any fault analysis tool known in theart such as EMMI, pico-probe station, IDS, sem, etc.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art semiconductor test system.

FIG. 2 shows a simple representation of an FA tool mounted over atester,

FIG. 3 is a block diagram of a test system in accordance with theinvention,

FIG. 4 is a diagram of one type of SERDES for use in the invention, and

FIG. 5 is a simple circuit diagram of a support circuit of oneembodiment of the invention for use with the SERDES of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 provides an overview of the test system in accordance with thepresent invention. In this case the tester 300 that provides the testvector signals to the motherboard 302 is located at a lab, which forconvenience will be referred to as the local location. In thisembodiment, the invention makes use of a test head that includes amotherboard 302 and socket 304 as known in the art. However, as is seenin FIG. 3, rather than mount a DUT in the socket 304, the DUT isseparated from the tester 300 and, instead, an adaptor board 310 isprovided that is adapted to be mountable on the socket 304. The adaptorboard 310 defines a communication means for communicating with theremotely located DUT. In this embodiment the adaptor board 310 includesa serializer-deserializer (SERDES) 312. The SERDES converts test vectorpattern data from the tester 300 to serial form for serial transmissionover communications line 320 to the remotely located DUT.

As mentioned above one feature of the invention is that the DUT 330 isremotely located and electrically connected to a virtual test head 332,which is described in greater detail below. It will be appreciated thatthe physical DUT will need means for receiving test vector pattern datafrom the tester 300 and for transmitting data received at the outputpins of the DUT, back to the tester 300. This is achieved in oneembodiment by mounting the DUT 330 in a socket 334 that is mounted on aboard 336 at the remote location. The board 336 is also provided with aSERDES 338, which receives serial test vector pattern data from theSERDES 312 and converts it to parallel form for the pins of the DUT 330.Parallel output data from the output pins of the DUT 330 are, in turn,converted by the SERDES 338 to serial form for transmission to theSERDES 312. Thus, one feature of the invention is that the tester 300and virtual test head 332, in this embodiment, are connected by a serialconnection 310 such as an intranet connection, e.g., Ethernet, orthrough an Internet connection. Thus, the physical communications linecan be any line or cable, e.g., coaxial cable, twisted pair, fiber opticcable, etc., that constitutes part of an intranet or the Internet.

As mentioned above, the virtual test head 332, which physically supportsthe DUT 330 does so by means of a socket 334 mounted on a PCB 336. Inthis embodiment the socket 334 is a 1024 pin socket for supporting DUTshaving up to 1024 pins. Since this embodiment contemplates use with avariety of DUTs with different I/Os, power supply pins and ground pins,additional circuitry is provided on the board 336 for tri-stating selectlines depending on whether they are input pins or output pins in thecase of a particular DUT. Also, the circuitry allows clocking signals tobe selectively applied to one or more pins, as is described in greaterdetail below.

FIG. 4 shows a block diagram of one type of SERDES provided by NationalSemiconductor Corporation, the DS92LV18 which provides a 2.376 Gbpsduplex throughput to support an 18 I/O pin device operating at 66 MHz.It will be appreciated that bandwidth limitations in the connection 320will limit the testing speed since one bit of data for one pin istransmitted with each clock cycle. As the number of pins for the DUTincreases to 1024 for instance, 1024 clock cycles are needed to providethe appropriate signals for all the pins for one test vector. It will,however, be appreciated that buffering of input data may be used toavoid retransmitting the same signal to a pin where the signal on thatpin remains unchanged from one vector to the next.

For ease of discussion an 18 I/O pin DUT will be considered. In order toallow output pins and select input/output pins of the DUT to betri-stated, additional circuitry is provides between the SERDES and theDUT as shown in FIG. 5. Serial data comes into the SERDES 500 frompositive and negative inputs 502 (since in this embodiment the serialconnection 320 is twisted pair) and is deserialized onto an 18 line databus 504. The 18 data or signal lines of the bus 504 are each providedwith a control block 506 before each is fed to a separate pin of the DUT508. In order to provide a clock signal to one or more pins of the DUT508, one of the 18 data lines of bus 504, in this embodiment, is fedinto a timing generator 510. The timing generator 510 could, forexample, simply be a function generator that makes use of the edgetrigger function of the function generator to generate a clock signal.The one data line 512 fed into the timing generator is, in thisembodiment, manually selected. It will be appreciated that a separate18:1 multiplexer could be included to allow the data line 512 to beselected.

As mentioned above, the control block 506 is instantiated 18 times (onefor each data line of the bus 504. The bus 504 is split into 18 separatelines, e.g., at point A, and each line 514 is fed into its own 2:1multiplexer 516. For each instantiation, the clock signal on line 512forms the other input to the multiplexer 516. This allows either thedata on the particular line 514 or the clock signal to be applied to apin of the DUT 508. In order to allow the lines into the DUT to betri-stated to avoid feeding signal into outputs of the DUT 508, eachline feeding into the DUT 508 is provided with a tri-state buffer 518.Each buffer 518 is controlled by one of the data lines of the bus 704,as determined by a 18:1 multiplexer 520. Thus the multiplexer 520 allowsindividual lines of the bus 504 to be selected, which, in turn eachcontrol a tri-state buffer 512. The output from the multiplexer 520 ishowever first fed into an AND gate 522, which has as its other input aselect signal 524, thereby controlling the throughput of the signal, inorder to accommodate bidirects. The output from the AND gate is thenused to control tri-state buffer 512.

While the above discussion dealt with 18 data lines and discussed onlydigital signals, the present invention is intended of DUTs with anynumber of I/Os and may also be used for analogue devices, in which theboards on either of the transmission would also include analog todigital (A/D) converters and digital to analog (D/A) converters. Also,as mentioned above, even though the above embodiment discussed serialtransmission using twisted pair, any medium and any protocol could beadopted to transmit the serial data. For example, HTTP drivers could beused of transmission over the Internet.

It will be appreciated that the invention can be used to reduce and evenavoid vibration from a tester while a DUT is being analyzed by a faultanalysis (FA) tool. This is achieved by mounting the virtual test headrelative to the FA tool and moving the tester some distance away orlocating it in an entirely different room or building and simplycommunicating serially between the tester and the virtual test head.

In situations where the DUT is not being analyzed by an FA tool, thepresent invention provides the convenience that the test engineer nolonger needs someone at the lab to place the DUT in the socket on thetester motherboard. Instead, the test engineer can have the virtual testhead in his or her office, mount the DUT on the virtual test head andcommunicate serially with the tester, which could be located at a remotelab.

1. A method of testing a semiconductor device (DUT) using a tester,comprising locating the DUT in a first DUT socket mounted on a firstboard at a remote location remote from the tester, and providingcommunication means for serially communicating between the tester andthe DUT for transferring information between the tester and the DUT, thetester including a second DUT socket and an adaptor board locatedremotely from the first board, the adaptor board being adapted to bemounted on the second DUT socket and including a serializer-deserializer(SERDES) as part of the communication means.
 2. A method of claim 1,wherein the information transferred from the tester to the DUT is testvector pattern data, and the information transferred from the DUT to thetester is output data from output pins of the DUT.
 3. A method of claim2, wherein the tester and DUT are connected by an intranet or Internetconnection.
 4. A method of claim 3, wherein providing the communicationmeans includes providing said serializer-deserializer (SERDES) locatedat the tester and providing a second SERDES located at the DUT.
 5. Amethod of claim 4, wherein the first DUT socket for the DUT and thesecond SERDES are mounted on a printed circuit board.